IEEE Projects

Software Application Projects

Non IEEE Project Domains

IEEE 2014 VLSI PROJECTS


S. No. Title Domain
1 Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems VHDL/VERILOG
2 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator VHDL/VERILOG
3 Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems VHDL/VERILOG
4 Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications VHDL/VERILOG
5 A Multicast Tree Router for Multichip Neuromorphic Systems VHDL/VERILOG
6 Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters VHDL/VERILOG
7 On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions VHDL/VERILOG
8 Switching Noise Improvement of a Limit-Cycle Amplifier Using a Negative Hysteresis Relay VHDL/VERILOG
9 Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement VHDL/VERILOG
10 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay VHDL/VERILOG
11 Time-Based All-Digital Technique for Analog Built-in Self-Test VHDL/VERILOG
12 Smart Reliable Network-on-Chip VHDL/VERILOG
13 Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip VHDL/VERILOG
14 On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors VHDL/VERILOG
15 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler VHDL/VERILOG
16 High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing VHDL/VERILOG
17 Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems VHDL/VERILOG
18 Colour histogram content-based image retrieval and hardware implementation VHDL/VERILOG
19 Resistive Threshold Logic TANNER
20 Recursive Approach to the Design of a Parallel Self-Timed Adder TANNER
21 Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration TANNER
22 Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress TANNER
23 Improved Accuracy Current-Mode Multiplier Circuits With Applications in Analog Signal Processing TANNER
24 Digitally Controlled Pulse Width Modulator for On-Chip Power Management TANNER
25 Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path TANNER
26 Area-Ef?cient Asynchronous Multilevel Single-Track Pipeline Template TANNER
27 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator TANNER
28 An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory TANNER
29 Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression TANNER